This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops fter a complete clock pulse. While the clock is low the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is high the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must notbe allowed to change while the clock is high. Data transfers to the outputs on the alling edge of the clock pulse. A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs.
74 Series IC's, IC / Transistors
74HC73 Dual JK Flip Flop IC
SKU:
689
Availability:
25 in stock
₹46.00 (Exc. GST)
25 in stock
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