The CD4027BC dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs. These flip-flops are edge sensitive to the clock input and change state on the positive going transition of the clock pulses. Set or reset is independent of the clock and is accomplished by a high level on the respective input.
- Wide supply voltage range: 3.0V to 15V.
- High noise immunity: 0.45 VDD (typ.).
- Low power: 50 nW (typ.).
- Medium speed operation: 12 MHz (typ.) with 10V supply.
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